1. Field of the Invention
This invention relates in general to a method of trench isolation in the manufacture of a CMOS transistor, and more particularly to a method of trench isolation which prevents latch-up of the CMOS transistor without using an epitaxial growth process.
2. Description of the Related Art
All CMOS circuits have a problem of latch-up which is induced by parasitic transistors. As shown in FIG. 1, a CMOS circuit consists of an NMOS transistor 21 formed in a P-type silicon substrate 10 and a PMOS transistor 19 formed in an N-well 11. In such a CMOS circuit, a parasitic bipolar transistor is easily formed. For example, within the PMOS transistor 19, a vertical PNP bipolar transistor is formed by the P.sup.+ drain-source (emitter), N-well 11 (base) and P-type silicon substrate 10 (collector). Similarly, within the NMOS transistor 21, a lateral NPN bipolar transistor is formed by the N.sup.+ drain-source (emitter), P-type substrate 10 (base) and N-well 11 (collector).
The vertical PNP bipolar transistor and the lateral NPN bipolar transistor are mutually coupled so that a thyristor is formed. If the current gain product of these two transistors is larger than 1, a large current will flow into the source from the drain whereby latch-up of the CMOS circuit is induced which causes temporary or permanent malfunctioning of the CMOS circuit
A method of preventing latch-up of a CMOS circuit is to enlarge the distance between the N-well and the N.sup.+ source-drain electrodes of the NMOS transistor, but this approach reduces the degree of integration of this integrated circuit component. Thus, the method popularly adapted to resolve the latch-up problem is an epitaxial process which is shown in FIGS. 2A through 2E.
As shown in FIG. 2A, an oxide layer 12 is deposited on a silicon substrate 10. Trenches 14, 16 are formed by etching predetermined positions of the substrate 10 such as where an N-well 11 and a field oxide layer 15 will be formed (see FIGS. 2C and 2D). In FIG. 2B, an insulating layer 18 is formed on the side walls of trenches 14 and 16 and N-type impurities such as phosphorus are implanted in the bottom of the trench 14, so that the silicon substrate beneath the trench 14 becomes heavily doped with N-type impurities.
As shown in FIG. 2C, trenches 14 and 16 are refilled by epitaxial growth. Under the trench 14, since the silicon substrate 10 is heavily doped with N-type impurities, the epitaxial silicon layer within the trench 14 provides the N-well 11. Under the trench 16, the silicon substrate is P-type. The epitaxial silicon layer within the trench 16 provides a channel-stop 13. As shown in FIG. 2D, then a field oxide layer 15 is formed. As shown in FIG. 2E, a PMOS transistor then is provided inside the N-well 11 and an NMOS transistor is provided in the P-type substrate. The oxide layer 18 is used for isolation.
Although the above mentioned method has the effect of preventing latch-up, it still has the following two deficiencies:
1. The epitaxial growth process is not easily performed in mass production. PA1 2. The epitaxial growth rate is not easy to control.